1. Field of Invention
This invention relates in general to a method of forming a shallow trench isolation (STI) region, and more particularly, to a method of making a shallow trench isolation region that has improved electrical characteristics, improved uniformity of the dielectric material which fills the trench, and improved uniformity during chemical mechanical polishing (CMP) operations.
2. Description of Related Art
The forming of a shallow trench isolation region for an electrical device includes performing anisotropic etching to form a trench in a semiconductor substrate, then filling the trench with an oxide material. In the manufacturing of submicron complementary metallic oxide semiconductors (CMOS), this is a preferred and scaleable isolation technique. The forming of STI regions is preferred over the formation of conventional local oxidation (LOCOS) structures, because STI regions do not exhibit a bird's beak encroachment. However, several technical problems need to be overcome before the use of shallow trench isolation regions becomes widely applied, for example:
(1) The uniformity of the dielectric material which fills the trench (for example, tetra-ethyl-orthosilicate (TEOS) formed using atmospheric pressure chemical vapor deposition (APCVD) methods) limits control of the thickness during chemical mechanical polishing operations.
(2) The wet etching may form grooves in the oxide layer near an edge of the shallow trench, which may cause a kink in the subthreshold voltage occurring in the surface channel of an n-type metallic oxide semiconductor (NMOS), thus increasing the current leakage below a threshold state.
(3) After filling the trench with the dielectric material, high temperatures generated during sealing processes may cause substrate defects that can lead to greater current leakage in the substrate of the final product.
FIGS. 1 through 12 are a series of cross-sectional views showing a conventional shallow trench isolation region being manufactured. Referring to FIG. 1, a pad oxide layer 101, used for protecting the surface of a silicon substrate 100 during subsequent processes, is formed on the silicon substrate 100. Then, a silicon nitride layer 102 is formed over the pad oxide layer 101 using chemical vapor deposition methods. Next, as shown in FIG. 2, a photoresist layer 103 is formed over the silicon nitride layer 102. Using photolithographic techniques, a shape as shown in FIG. 2 is formed. Referring to FIG. 3, the silicon nitride layer 102, pad oxide layer 101, and silicon substrate 100 are sequentially etched to form a shallow trench 104. Next, the photoresist layer 103 is removed.
Referring to FIG. 4, in a subsequent step a side-wall oxide layer 105 is grown on the surface of the silicon substrate 100 within the shallow trench 104. Thereafter, as shown in FIG. 5, a silicon oxide layer 106 is deposited and fills the shallow trench 104. For example, TEOS is formed in the trench using an APCVD method. Then, a sealing operation is performed at a high temperature for approximately ten minutes. However, due to the height of the silicon oxide layer 106 (which projects beyond the boundaries of the trench), the sealing operation may cause substrate defects. Using the silicon nitride layer 102 as a polishing end point, chemical mechanical polishing (CMP) is performed to remove excess portions of the silicon oxide layer 106, thus resulting in the cross-section shown in FIG. 6.
Referring to FIG. 7, silicon nitride layer 102 is removed, thus exposing pad oxide layer 101 while leaving behind silicon oxide layer 106. Then, pad oxide layer 101 is removed by immersing the layer 101 in a hydrofluoric acid (HF) solution. Concurrent with the removal of pad oxide layer 101, a portion of silicon oxide layer 106 is etched to obtain the cross section shown in FIG. 8.
Referring next to FIG. 9, a sacrificial oxide layer 107 is grown on the silicon substrate 100 and serves as a protective layer. Thereafter, an ion implantation procedure is performed to create a well 108, which may be, for example, a P-type well or an N-type well. The sacrificial oxide layer 107 is then removed by immersing the layer 107 into the hydrofluoric acid solution, thus forming the cross-section shown in FIG. 10. This operation often causes the formation of grooves 109 near the wall edges of the trench.
Referring to FIG. 11, using a high temperature, a gate oxide layer 110 is grown over the silicon substrate 100. A polysilicon layer 111 is then deposited over silicon substrate 100 using a chemical vapor deposition method. Using photolithographic and etching processes, polysilicon layer 111 is shaped as shown in FIG. 12 to form polysilicon gate 111'. Because polysilicon gate 111' lays across gate oxide layer 110 and oxide layer 106, a portion of the gate may cover the oxide grooves 109, thus causing a kink to occur in the subthreshold voltage.
An NMOS transistor having a gate oxide layer thickness of 60 .ANG., drain voltage of 0.1 V, channel width of 10 mm, channel length of 0.25 mm, and a substrate voltage between 0 and -4 V, was provided and tested to determine the relationship between drain current and the gate voltage when the aforementioned kink in the subthreshold voltage was present. The results are shown in FIG. 13. The relationship between the drain current and the gate voltage in the absence of such a kink is shown in FIG. 14. As shown in FIG. 13, the kinked region in the graph is a result of disadvantageous subthreshold voltage distortion.